Recently, there is a trend for increasing memory usage in application specific integrated circuits (ASICs). The Semiconductor Industry Association (SIA) estimates that, by the year 2014, a typical ASIC will comprise about 94 percent memory (by die area). The trend is also for decreasing the size of memories, which are often implemented as latch-based random access memory (LBRAM). However, an important issue with the use of such a large number of LBRAMs is the amount of die area occupied by the memories.
It is common to use static random access memories (SRAMs) within ASICs. SRAMs typically comprise bit lines, word lines and an array of special memory cells, also referred to herein as bit cells, surrounded by specialized circuitry to read data from and/or write data to the array. The memory cells are often organized in groups such that all cells in a given group are coupled to a common bit line. The bit lines are used to write data into the memory cells and to read data from the memory cells.
Typically, the bit lines in SRAMs do not use the same voltage levels to represent a logic “1” or “0” data state as do standard ASIC logic cells. Rather, there is a much smaller voltage differential between a “1” and a “0” data state, and special sense amplifier circuits are generally required to determine whether the bit line is reading a “1” or a “0” data state from a selected memory cell coupled thereto. Using a small voltage differential has an advantage of allowing a smaller memory cell and faster transition times on the bit line. However, a disadvantage is that the sense amplifier circuits add significant area overhead, which can be a large drawback for small memories. Furthermore, SRAMs are more susceptible to IC process defects than standard logic circuitry and may require special built-in-self-test (BIST) logic to test for such defects. For smaller memories, the area of the BIST logic may be larger than the memory itself.
Due to the excessive area of SRAMs, small memories are often implemented as LBRAMs. However, although a memory implemented using LBRAMs generally consumes less die area compared to SRAMs, it is still beneficial to reduce the area requirements of a LBRAM cell to reduce overall die area and cost of the IC. If latches in the memory array are placed as densely as possible, the number of signal wires would essentially completely use all available space above the array. As a result, there would be no room to place required connections between the individual memory cells and power rails in the IC. Consequently, in standard LBRAMs, the latches are placed less densely to allow room for power rail connections, thereby increasing the die area of the IC.